CTS is the process of insertion of buffers or inverters along the clock paths of ASIC design in order to achieve zero/minimum skew or balanced skew. The goal of CTS is to minimize skew and insertion delay. Apart from these, useful skew is also added in the design by means of buffers and inverters. Note: In […]
Category Archives: ASIC Back-End
Floor planing is the starting step in ASIC physical design. For example, before building the house, planning for the exact location of each end every room is similar to the ASIC’s floor planning process. Building’s blue-print planning will be a better example for ASIC floor planning. Kitchen and the dining room will be communicated with […]
asic back-end 