ASIC Floor Planning

Floor planing is the starting step in ASIC physical design. For example, before building the house, planning for the exact location of each end every room is similar to the ASIC’s floor planning process. Building’s blue-print planning will be a better example for ASIC floor planning. Kitchen and the dining room will be communicated with each other very often and those two rooms should be kept close to each other and similarly, modules to be communicated very often are to be placed very close in order to reduce the routing resources. Detailed process of floor planning is explained below with necessary diagrams.
Floor plan determines the size of the design cell (or die), creates the boundary and core area, and creates wire tracks for placement of standard cells. It is also a process of positioning blocks or macros on the die. First step is to define the total size of the die. Two types of design are possible. Block level designs will be rectilinear and chip level designs will be rectangular in shape.

• Rectilinear – To define this size more coordinates are required
• Rectangular – To define this only height and width of the die is required

The following parameters are decided in the floor planning stage.

• Die size, core size of the chip (rectangular or rectilinear)
• I/O pad’s location
• Plan for power
• Row configuration

In broader sense pad info, power planning and macro placement together is known as floor planning. Apart from this aspect ratio of the core , utilization of the core area,  cell orientation and core to I/O clearance are also be taken care during the floor plan stage.

Aspect Ratio= Width of the die / Height of the die

Utilization:Utilization defines the area occupied by standard cell, macros and blockages. In general 70 to 80% of utilization is fixed because more number of inverters and buffers will be added during the process of CTS (Clock Tree Synthesis) in order to maintain minimum skew.

Note: The buffers and inverters to be added during the CTS process should have equal raise and fall time in order to avoid the change in time period or duty cycle of the clock signal which in turn changes the operating frequency of a design.

Row Orientation: These rows are individual rows and  the row area is utilized by the standard cells as shown below in figure 1. As mentioned above in the formula, the utilization factor is decided by the channel area also. If the channel area is reduced, better the utilization can be achieved.

fig-1: Row orientation

But reducing the channel area leads to short between Vss and Vdd. To avoid this, every rows are flipped so that Vdd of two rows can be joined together and Vss of two rows can be connected together and there will be no chance in short between Vdd and Vss as shown in figure-2. The utilization depends only on the row area, not the channel area.

fig-2: Double-back rows

Cell Orientation
Macros placement is done manually based on the connectivity with other macros and also with I/O pads. Macros are moved on the basis of connectivity and the orientation of macros are as shown below in figure-3.

fig-3: Cell orientation

from the figure-3,

a –> R0 — No rotation
b –> MX — Mirror through X axis
c –> MY — Mirror through Y axis
d –> R180 — Rotate counter-clockwise 180 degrees
e –> MX90 — Mirror through X axis and rotate counter-clockwise 90 degrees
f –> R90 — Rotate counter-clockwise 90 degrees
g –> R270 — Rotate counter-clockwise 270 degrees
h –> MY90 — Mirror through Y axis and rotate counter-clockwise 90 degrees

By using the flight/fly lines the exact connectivity of macros to other macros or I/O pads can be seen and with the help of these orientations, the cell’s physical orientation can be changed and as a result of this routing resources can be reduced. The concept of flight/fly lines is given below.

Fly Lines

Fly/flight lines are virtual connections between macros and also macros to I/O pads. This helps the designer to get an idea about the logical connections between macros and pads. Fly/flight lines act as guidelines to the designer to reduce the routing resources to be used. On the basis of connectivity it shows, flight lines are of three types.

1. Macro to macro fly lines
2. pin to pin fly lines
3. macro to I/O fly lines

Macro to macro fly lines

This shows the total number of connections between two macros. This gives an idea to the designer about which two modules to be placed closer.

Pin to pin fly lines

If two macros are selected for pin to pin fly lines, the virtual connections are shown  and the much preciously connection to exact pin to pin will be shown. This guides the designer to choose an appropriate cell orientation (fig-3) for the macros and as a resultant will be efficient routing.

Macro to I/O fly lines

Macro to I/O flight lines shows the exact connection between the macro pins and the I/O ports of pins. This helps the designer to identify the macros to be kept at the corners of the die or block.

Pictorial representation these flight lines and the how these lines act as guidelines to the designer is shown below in figure-4.

fig-4: Fly lines

From the figure

i) macro to macro fly lines
ii) pin ti pin fly lines
iii) for B macro “R90” is applied (B is rotated 90 degrees to the anti-clock direction)
iv) for A macro “R180” is applied (A is rotated 180 degrees to the anti-clock direction)

This is how the fly lines acts as guidelines for macro placement. In a similar way macro to I/O fly lines also helps the designer to identify the macro to be placed in the corners.

Core to IO Clearance: Distances from core to I/O pads are mentioned manually. Figure-5  shows the core to I/O clearances. This distance from core to I/O purely depends on the width of Vdd and Vss metal layers.

fig-5: core to I/O clearance

Pad Limited Design

• If pad area is more than core area
• Large number of I/O pads and less number of logic I/O pads
• Here pad area decide the size of the die

Core Limited design

• If core area is more than pad area
• Core area decides the die size

Bond Pads

Pad placements are of two types.

Inline Bonding

• All pads are of same height
• Generally used in most of the designs
• Can be used when design is not pad limited

Staggered Bonding

• Pads are of different heights
• Can be used when design is pad limited

Corner Cells

• I/O pads are not placed in corner of the chip
• To fill the gap and to provide I/O pad power ring connectivity corner cells are used
• It doesn’t perform any logic or they doesn’t contain any CMOS circuitry, they are added to maintain the  connectivity for I/O pad power rings

Filler Cells

• Similar to corner cells
• Used for continuity of pad power ring