CTS (Clock Tree Synthesis)

CTS is the process of insertion of buffers or inverters along the clock paths of ASIC design in order to achieve zero/minimum skew or balanced skew. The goal of CTS is to minimize skew and insertion delay. Apart from these, useful skew is also added in the design by means of buffers and inverters.

Note: In order to achieve positive slack or zero slack intentionally some skew is introduced into the design by adding buffers or inverters or by up-sizing the cells. This is called as useful skew. 

Clock is propagated after placement because the exact physical location of cells and modules are needed for the clock’s propagation which in turn impacts in dealing with accurate delay and operating frequency and clock is propagated before routing because when compared to logical routes, clock routs are given more priority. This is because, clock is the only signal switches frequently which in acts as source for dynamic power dissipation.

Note: Buffers and inverters to be added into the design during the clock tree synthesis must have equal raise and fall time delay. If not, it will affect the time period/duty cycle of clock which in turn changes the operating frequency. 

Though wide range of clock routing algorithms are available, EDA tool chooses the optimized algorithm automatically and it only shows the critical paths after propagating the tree. If a design results in negative slack, increasing the clock timing is an easy way but changing the clock period changes the operating frequency. Solving the negative slack without changing the clock period is possible by up-sizing or down-sizing the cell in critical paths.

CLOCK TREE BEGIN AND END

• Clock tree begins at SDC (Synopsys Design Constraints) defined clock source
• Clock tree ends at clock pins of FF or hard macros or input pins of combinational logic also.

As mentioned above clock will also be given to input pin of combinational block but very rarely in low power techniques such as clock gating etc. On the basis of the clock tree begin and end point important terminologies are derived as mentioned below.

Terminologies and Definitions in CTS 

• Stop (Sync) Pins: All clock pins of FF are called as Stop (Sync) Pins. The clock signal  should not propagate after reaching the syc/stop pin. This pin needs to considered for building the clock tree.
• Exclude (Ignore) pins: All non clock pins such as D pin of FF or combo logic’s inputs are called as Exclude (Ignore) pins. These pins are need not to be considered during the clock tree propagation.
• Float (Implicit stop or macro model) pins: This is same as sync or stop pin but internal clock latency of that pin is taken into consideration while building the clock tree. Its a clock entry pin of hard macros and it needs to be considered while building the clock tree. But before considering this as sync pin, the macro’s internal tree needs to be balanced.
• Explicit sync (stop) pins: Input of a combo logic is considered while building the clock tree. Mostly this comes to picture  whenever clock gating concept is used.
• Explicit Exclude (Ignore) pins: Clock pin of a flip flop is not considered as sync/stop pin. This is also again due to the use of clock gating concept. Because while gating the clock, the clock signal will be given to an and gate.

fig-1: CTS Terminologies

Pictorial representation of terminologies are shown in figure-1 as shown above.