CTS is the process of insertion of buffers or inverters along the clock paths of ASIC design in order to achieve zero/minimum skew or balanced skew. The goal of CTS is to minimize skew and insertion delay. Apart from these, useful skew is also added in the design by means of buffers and inverters. Note: In […]
Monthly Archives: December 2012
CTS (Clock Tree Synthesis) process is carried out after placement of macros and standard cells, because only after placement of cells the exact physical location of cells can be identified which is needed to establish the tree structure in the design. CTS process is carried out before routing, because clock’s routes are to be given […]
asic back-end 